`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/17/2021 10:06:18 PM
// Design Name: 
// Module Name: main_workmode_module
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module main_workmode_module(
    input clk,
    input rst_n,
    input key_change,
    input [3:0] out0,
    input [3:0] out1,
    input [3:0] out2,
    input [3:0] out3,
    input [3:0] work0,
    input [3:0] work1,
    input [3:0] rest0,
    input [3:0] rest1,
    output [3:0] fin0,
    output [3:0] fin1,
    output [3:0] fin2,
    output [3:0] fin3,
    output en_fun,
    output en_config
    );
    wire key_value,key_p,key_n;

    eliminator elimin1(
        .rst_n(rst_n),
        .clk(clk),
        .key(key_change),
        .key_value(key_value),
        .key_p_flag(key_p),
        .key_n_flag(key_n)
    );
    workmode work_mode(
        .clk(clk),
        .rst_n(rst_n),
        .key_change(key_n),
        .out0(out0),
        .out1(out1),
        .out2(out2),
        .out3(out3),
        .work0(work0),
        .work1(work1),
        .rest0(rest0),
        .rest1(rest1),
        .fin0(fin0),
        .fin1(fin1),
        .fin2(fin2),
        .fin3(fin3),
        .en_fun(en_fun),
        .en_config(en_config)
    );
endmodule
